1. Field of the Invention
The present invention relates generally to semiconductor integrated circuit devices, and more particularly to a technology of a higher degree of integration of a semiconductor integrated circuit device having a stacked capacitor.
2. Description of the Related Art
In recent years, in order to apply the technique of microelectronics to industrial machinery and home appliances, a VLSI (Very-Large-Scale Integration) circuit which is a higher integrated LSI (Large Scale Integration) has been developed and are commercially available. In the case of a semiconductor memory device especially, the storage capacity has been increased thousand-fold in the last decade. The development of such high integration is realized by miniaturization of the size of a unit storage element, which constitutes a semiconductor memory device, by using a method called a proportional scaling.
As an example, a Dynamic Random Access Memory (DRAM) will be described in the following. A DRAM stores information as electric charges stored in a capacitor. As the stored charges leak and decrease, a refresh operation is required periodically in the DRAM. It is possible in the DRAM to access information at a definite access time regardless of the location of the information.
In the DRAM, a memory cell region is inevitably reduced with the miniaturization. The amount of charge which can be stored in the memory cell region with the same structure decreases with the reduction in the area of memory cells. With the advancement of the miniaturization, the amount of charge stored in the memory cells becomes extremely small, resulting in a marked degradation in reliability due to soft error or the like.
To cope with that problem, various improvements have been attempted for increasing a storage capacitance of the memory cells.
A three-transistor DRAM cell will be described in the following. After that, an application of a stacked capacitor to the three-transistor DRAM will be described.
Referring to FIG. 1, the DRAM includes: a memory cell array 1000 including a plurality of memory cells constituting a storage section; a row decoder 2000 and a column decoder 3000 connected respectively to a row address buffer 2100 and to a column address buffer 3100 for selecting the address of the DRAM; a control circuit 4000 for controlling the operation of the DRAM; and an input/output interface including sense amplifiers 1100 connected to an input/output circuit.
Referring to FIG. 2, a plurality of memory cells MC are disposed in a matrix form having a plurality of rows and columns. Each memory cell MC is connected to a corresponding reading selection line 120 and a writing selection line 110 connected to the row decoder 2000, and to a corresponding data-in line 108 and data-outline 121 connected to the column decoder 3000 through the sense amplifiers 1100, to constitute a memory cell array 1000.
In response to the externally applied row address signal and column address signal, a reading or writing selecting line 120, 110 and a data-in or data-out line 108, 121 are selected respectively with the row decoder 2000 and the column decoder 3000. A memory cell MC is selected with the selected lines. The externally applied data are stored in the selected memory cell MC. Or the data stored in the memory cell MC are read out of the same. The read/write instruction of the data is controlled by a read/write control signal given to the control circuit 4000.
Assuming that the memory cell array 1000 has n word lines and m bit lines, the memory cell array 1000 can store N (=n.times.m) bit data. The address of the memory cell, to which the data are to be written or from which the data are read out, is retained in the row address buffer 2100 and the column address buffer 3100.
M bits of the memory cells are connected to the sense amplifiers 1100 through data-in or data-out lines 108, 121 by the selection of a specific reading or writing selection line 120, 110 by the row decoder 2000 (selection of one word line out of n word lines). One sense amplifier out of the connected sense amplifiers 1100 is connected to the input/output circuit by the following selection of a specified data-in or data-out line 108, 121 by the column decoder 3000 (selection of one bit line out of m bit lines). Readout or writing is operated in the memory cell MC connected to the input/output circuit following the instruction from the control circuit 4000.
FIG. 3 is a circuit diagram of one example of a memory cell of the three-transistor DRAM. Referring to FIG. 3, the memory cell is connected to a writing selection line 110, a reading selection line 120, a data-in line 108 and a data-out line 121. The memory cell includes three N channel MOS transistors 11, 12 and 22.
The transistor 11 includes a transfer gate 4 connected to the writing selection line 110 and a source connected to the data-in line 108. The transistor 12 includes a storage gate 14 connected to a drain of the transistor 11, and a drain connected to ground 123. The transistor 22 includes a gate connected to the reading selection line 120, a drain connected to a source of the transistor 12, and a source connected to the data-out line 121.
An operation of the three-transistor DRAM will now be described with reference to FIG. 3. In data writing, a potential of "H" or "L", corresponding to data to be written into the cell, is supplied to the data-in line 108. The potential of "H" is supplied to the writing selection line 110. The potential of the transfer gate 4 of the transistor 11 attains "H", so that the transistor 11 is turned on. Charge corresponding to a potential on the data-in line 108 is stored in the storage gate 14 of the transistor 12.
With a potential on the writing selection line 110 attaining "L", the transistor 11 is turned off. Charge corresponding to write-in data remains in the storage gate 14, so that the writing is completed.
The data is held as the stored charge in a gate capacitance of the storage gate 14. Therefore, this RAM cell is of dynamic type, which requires a refresh operation.
In the DRAM cell in FIG. 3, data is stored as charge in the capacitance of the storage gate 14 of the transistor 12, as described above. Since the storage gate 14 is capacitively coupled to the drain or source of the transistor 12, the potential of the storage gate 14 is easily affected by a fluctuation in the potential on the drain or source. Data is liable to be destroyed due to soft error or the like because only a small amount of charge is stored on the gate capacitance. Also in data reading, a small potential difference results in a lower reliability in operation. In addition, the smaller capacitance also requires a frequent repetition of the refresh operation.
It is effective to add a capacitor to the memory cell for increasing the storage capacitance. FIG. 4 is an enlarged circuit diagram with a supplemental capacitance of a dashed-box A of FIG. 3. FIG. 5 is a section of the structure of a semiconductor integrated circuit device corresponding to FIG. 4. The common reference numerals in FIGS. 5 and 6 denote the same or corresponding portions.
Referring to FIGS. 5 and 6, the circuit A includes a N channel transistor 11 formed on the main surface of a P type semiconductor substrate 7, a capacitor 15 connected to a drain of the transistor 11, a transistor 12 formed in a region on the main surface of the substrate 7, which is isolated from the transistor 11 and the capacitor 15 by the isolation region 6, and an interconnection 16 made of polysilicon or metal for connecting the drain of the transistor 11 and the gate of the transistor 12.
The transistor 11 includes N.sup.+ impurity regions 5a, 5b spaced apart from each other on the main surface of the substrate 7, and a transfer gate 4 made of polysilicon, formed on the main surface of the substrate 7 between the impurity regions 5a and 5b. A gate oxide film is sandwiched between the gate 4 and the main surface of the substrate 7.
The capacitor 15 includes a storage node 1 made of
polysilicon, connected to the impurity region 5b through the contact hole 18, a thin dielectric film 3 formed on the storage node 1, and a cell plate 2 made of storage node 1. The impurity region 5b is formed between the transfer gate 4 and the isolation region 6.
The transistor 12 includes N.sup.+ impurity regions 5c and 5d formed, spaced apart from each other, in a region on the main surface of the semiconductor substrate 7, which is isolated by the isolation region 6 from the region where the transistor 11 is formed, and a storage gate 14 formed on the main surface of the substrate 7 between the impurity regions 5c and 5d. A gate oxide film is sandwiched between the gate 14 and the main surface.
The interlayer insulation film 22 is formed on the memory cell, and the data-in line 108 made of polysilicon or metal is formed on the interlayer insulation film 22. The interconnection 16 is connected to the impurity region 5b through a contact hole 17a formed in the interlayer insulation film 22, and is connected to the storage gate 14 through a contact hole 17b. The data-in line 108 is connected to the impurity region 5a through a contact hole 9 formed in the interlayer insulation film 22.
Referring to FIG. 5, a plurality of elements can be provided on the main surface of the substrate 7 between the impurity regions 5b and 5d.
The operation of the memory cell of the three-transistor DRAM described above is identical to that of the memory cell of the three-transistor DRAM with no capacitor which is already described. Therefore, a detailed description thereof will not be repeated here. An improvement in this device is that since the stacked capacitor 15 is provided in the memory cell, the storage capacitance of the memory cell is considerably increased. This enables an enhancement in data holding capability and a reading reliability of the memory cell.
An application of the above-described stacked capacitor to the semiconductor integrated circuit devices other than the DRAM will be described in the following. A dynamic CAM (Content Addressable Memory) having stacked capacitors is taken as an example.
FIG. 6 is a schematic block diagram of a common CAM. Referring to the figure, the CAM includes a CAM array 5000 as a storage region including an arrangement of CAM cells which are unit storage elements, m-bit data register 7000 to which data to be written in the CAM array 5000 or data to be compared with a content stored in the CAM array 5000 is externally supplied, an address decoder 6000 for selecting one of n word lines in the CAM array 5000 in response to an externally applied address signal, a match line sense amplifier 5100 for amplifying a signal appearing on a match line provided for each word of the CAM in data search, a search output register 5200 for storing an output of the match line sense amplifier 5100, and an address encoder 5300 for outputting a stored address of data searched for.
Since the CAM array 5000 is defined by m bit lines and n word lines, the CAM array 5000 can store binary data of n words.times.m bits.
FIG. 7 schematically shows the arrangement of the CAM cells in the CAM array 5000. Referring to the figure, the CAM array 5000 includes a plurality of bit lines 8a and inverted bit lines 8b, alternately arranged transversely and extending longitudinally, a plurality of word lines 10 and match lines 19, alternately arranged longitudinally and extending transversely, and CAM cells 20 each provided in a region enclosed by a pair of the bit lines 8a and 8b and by a pair of the word line 10 and match line 19, and connected to the bit line pair 8a, 8b, the word line 10 and the match line 19. The match line sense amplifier 100 is connected to one end of the match line 19.
An outline of the operation of the CAM will now be described with reference to FIGS. 7 and 8. In writing, the following operations are sequentially carried out.
(1) Write-in data (m-bit width) is inputted to the data register 7000.
(2) Data in the data register 7000 is applied to all the bit line pairs 8a, 8b in the CAM array 5000.
(3) An external address signal (in a log.sub.2 n-bit width) is inputted to the address decoder 6000, so that the address is decoded to select the corresponding word line.
(4) A potential of "H" is applied to the corresponding word line 10. Data of each of the bit line pairs 8a, 8b, is written into the corresponding CAM cell 20 connected to the selected word line 10.
(5) The potential on the word line 10 is again lowered to "L".
Writing the data into the CAM is here completed, following the above procedure. A detailed method of data storage in the CAM 20 will be described later.
A search operation is one of important functions of the CAM. In the search operation, data previously stored in the CAM array 5000 is compared with search information supplied to the data register 7000, so that an address of data matching with the search information is outputted from the address encoder 5300. The search operation includes the following procedure.
(1) Search information (m-bit width) is inputted to the data register 7000.
(2) Data in the data register 7000 is applied to all the bit line pairs 8a, 8b in the CAM array 5000.
(3) Stored information in each word is compared with the search information applied to the bit line pairs 8a, 8b with respect to n words of the CAM array 5000. The result of the comparison is outputted onto the match line 19.
(4) The match line sense amplifier 5100 amplifies the result of the search outputted onto the match line 19 of each word.
(5) The searched result amplified by the match line sense amplifier 5100 is written into the search output register 5200 for each word. At this time, only the register for the word, in which the stored information and the search information coincide with each other, is set.
(6) The address encoder 5300 outputs an address for the word, in which the stored information and the search information coincide with each other, in response to an output of the search output register 5200.
The reading operation in the CAM will not be described here because such an operation is unnecessary.
One example of the dynamic CAM is proposed in "IEEE Journal of Solid-state Circuits" (Vol. SC-7, pp. 366). Another example is proposed in Japanese Patent Laying Open No. 63-91898. The latter is supposed to be an improved version of the former. That is, the latter has supplemental capacitance whereas the former has none.
Referring to FIG. 8, the memory cell 20 is connected to the word line 10, the bit line 8a, the inverted bit line 8b and the match line 19. The memory cell includes five n channel MOS transistors 11a, 11b, 12a, 12b and 13 and two capacitors 15a and 15b. The transistors 11a and 11b have respective gates 4a, and 4b connected to the word line 10. Respective sources of the transistors 11a and 11b are connected to the bit line 8a and the inverted bit line 8b.
The transistors 12a and 12b have storage gates 14a and 14b connected to drains of the transistors 11a and 11b, respectively. Sources of the transistors 12a and 12b are connected respectively to the bit line 8a and the inverted bit line 8b. A source of the transistor 13 is connected through a node 21 to respective drains of the transistors 12a and 12b.
The transistor 13 has its gate and drain both connected to the match line 19. The transistor 13 functions as a diode.
The capacitors 15a and 15b are connected to the drains of the transistors 11a and 11b, respectively.
A description will be given on writing of data into the above-described CAM cell 20 and on a searching operation of data stored in the CAM cell 20.